Mr. Peter Copetti reports

POET TECHNOLOGIES ANNOUNCES AN UPDATE ON THE "LAB-TO-FAB" TRANSITION AND THE 100-NM AND 40-NM SCALING PROGRAM

Poet Technologies Inc. has provided an update on its "Lab-to-Fab" transition and its 100-nanometre and 40-nanometre scaling program.

Lab-to-Fab transition: 100-nanometre and 40-nanometre scaling program update

The company recently reported a contractual effort with a third party foundry to accelerate the transition from Lab-to-Fab of the planar opto-electronic technology to a manufacturing status at the six-inch wafer scale. The target of the effort is 40-nanometre dimensions for the critical features. This engagement will support and enhance the development and verification of the foundation devices and design enablement kits. Additionally it will provide the baseline front-end-of-line process flow in a manufacturing environment and toolset. Fabrication at 40-nanometre (silicon CMOS) is a mature semiconductor process that has been in existence since 2007-2008. This enables Poet to target a mature process flow and revitalize existing manufacturing lines while delivering predicted performance and power efficiencies that rival today's state-of-the-art process node in the sub-20-nanometre range (silicon CMOS). This effort will enable and progress two of the company's current key initiatives which the company is currently working on: a 100-nanometre ring oscillator which is a common demonstration vehicle for performance and an integrated 50-gigahertz VCSEL device, both targeted for the first quarter of 2015.

Recently, milestone goals and their associated target completion dates have been adjusted to align to potential customer demands. Peter Copetti, executive chairman and interim chief executive officer, noted: "It is important for us to remain flexible in setting design targets to the market. The company is focused on delivering to its potential customers the technology nodes that will enable them to leapfrog their competition. Our Lab-to-Fab transition and our new 40-nanometre target node will deliver just that: a road map for integrating electrical and optical capabilities, performance and power efficiency."

Operational updates

The company is anticipating delivery of the 40-nanometre PET process design kits by the end of the year. The company is using Synopsys TCAD tools and services to develop the PET and Poet PDKs. PDKs are used by third party chip developers to create IP libraries that would be used to implement system-on-chip integrated circuits. Availability of the PDKs will enable early evaluation of the performance advantages of Poet technology and design of IP required for SoC implementation. Daniel DeSimone, the company's chief technology officer, noted: "We are encouraged by our progress on the PDK development and our level of collaboration with the Synopsys team. This level of modelling is synergistic to our parallel efforts with our third party foundry on the development of 100-nanometre and 40-nanometre process flow."

The company's website and its corporate presentation have been updated to highlight the new targets set forth from the management team that reflect customers and market expectations. The value proposition of the company is strong with the new 40-nanometre feature size target predicted to operate four nodes better in logic performance and three nodes better in power consumption compared with silicon CMOS. The density is expected to be comparable and possibly better, as Poet requires less buffering and upsizing of logic cells. The Poet process offers the ability to have digital, analog and mixed signals, and optical devices, on the same die or chip. Those capabilities would allow designs of complex systems and systems on a chip to deliver innovations and integration that are impossible today with existing processes in the market. This process node also takes advantage of existing and mature manufacturing capabilities already available in the industry.

Executive staff update

The company announces the promotion of Stephane Gagnon to chief operating officer of the company. Mr. Copetti writes: "Stephane brought a steady and focused winning attitude to our executive team. His diligent work and attention to details make him an ideal fit for this role." The company also announces that Lee Shepherd, vice-president of technology will be leaving the company effective Oct. 31. Mr. Copetti continues: "We want to thank Lee for his many contributions to Poet over the last two years. Lee was a very important part of our executive team that led the turnaround for Poet."

Facility update

The company has recently established a satellite office in Silicon Valley, San Jose, Calif. Mr. Gagnon notes: "We are excited to finally have an interim office in Silicon Valley while negotiations are under way for a permanent office. It is important to have a presence in the valley because the majority of our potential customers and partners are located there. Our executive vice-chairman, Ajit Manocha, is based in the heart of the Silicon Valley and is already active in engaging with potential strategic partners and stakeholders."

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