Mr. Peter Copetti reports

POET ANNOUNCES A COLLABORATION WITH THIRD PARTY FOUNDRY TO REPRODUCE AND ENHANCE REPEATABILITY OF THE 100-NM RESULTS AND SHRINK ITS PLANAR ELECTRICAL TECHNOLOGY PROCESS (PET) TO 40-NM SCALE

Poet Technologies Inc. has made an agreement with a third party foundry to reproduce and enhance repeatability of the 100-nanometre-scale results obtained at the company's labs located at the University of Connecticut. The third party foundry will also assist the Poet team in shrinking the 100-nanometre PET devices and process to a 40-nanometre feature size.

Having developed a structure suitable for scaling Poet transistors to the 100-nanometre scale, Poet has actively engaged a third party foundry to replicate the Poet results with greater precision and larger scale using advanced ebeam writing tools. Definition and repeatability of 100 nanometres have been difficult in the Poet labs due to the limitations of available lithography tools and other equipment. The collaboration gives the Poet team access to superior capability and diagnostics, allowing the Poet approach to start to scale to both three-inch and six-inch wafers with much larger device count and across wafer alignment. The fine features will then be merged with optical lithography and other procedures necessary to transition to a manufacturing environment. In addition, the effort will target line width reductions from 100 nanometres down to 40 nanometres, which should enable Poet performance parameters to compete with present state-of-the-art processes. The reduction will be parallel to the company's efforts with its Synopsys TCAD collaboration.

Dr. Geoff Taylor, chief scientist and board member, noted: "Developing the 100 nm feature size technology in the current Poet labs has proven to be challenging. With the collaboration of our third party foundry, we now have access to state-of-the-art equipment highlighted by a state-of-the-art ebeam writing tool. This will help us make the process more stable and predictable and help prove our process in a true manufacturing environment."

This announcement follows another announcement today from the company regarding collaboration with Synopsys and the creation of the company's first process design kit. This collaboration will see the development of an advanced model of the company's PET devices targeting a technology node of 40 nanometres, a significant production node of highly integrated systems-on-chip silicon CMOS device. The results of the physical devices at 40 nanometres developed at the third party foundry can then be correlated to the models of the PET technology developed using TCAD tools from Synopsys and vice versa.

Peter Copetti, executive chairman and interim chief executive officer, concluded: "We now believe we have the right collaboration in place with Synopsys and our third party foundry to model our technology down to 40 nm and correlate our process to real physical device measurements. This should provide us with results needed to showcase our technology to potential customers at the optimum node for our platform. We expect synergistic benefits from having parallel operations with the same end target."

We seek Safe Harbor.